Digital Design of 16 - Bit Carry Look Ahead Adder ( Circuit + Verilog HDL)

16 Bit Carry Look-ahead Adder:

- In last blog we discussed about 4 bit carry look-ahead adder - 4 bit Carry Look-ahead Adder

- Connecting four instances of 4-bit carry look-ahead adder will result in a 16 Bit Carry Look-ahead Adder

Block Diagram of 16 Bit Carry Look-ahead Adder:

     

Verilog HDL Code:

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`include "carry_look_ahead_adder_4_bit.sv"

module carry_look_ahead_adder_16_bit(a_in, b_in, carry_in, sum_o, carry_o);

  input [15:0] a_in;

  input [15:0] b_in;

  input carry_in;

  output [15:0] sum_o;

  output carry_o;

  wire c1, c2, c3, c4;

  carry_look_ahead_adder_4_bit   CLA1(.a_in(a_in[3:0]), .b_in(b_in[3:0]), .carry_in(carry_in), .sum_o(sum_o[3:0]), .carry_o(c1)); 

  carry_look_ahead_adder_4_bit   CLA2(.a_in(a_in[7:4]), .b_in(b_in[7:4]), .carry_in(c1), .sum_o(sum_o[7:4]), .carry_o(c2)); 

  carry_look_ahead_adder_4_bit   CLA3(.a_in(a_in[11:8]), .b_in(b_in[11:8]), .carry_in(c2), .sum_o(sum_o[11:8]), .carry_o(c3)); 

  carry_look_ahead_adder_4_bit   CLA4(.a_in(a_in[15:12]), .b_in(b_in[15:12]), .carry_in(c3), .sum_o(sum_o[15:12]), .carry_o(c4));  

  assign carry_o = c4;

endmodule

// Code your design here

`include "full_adder.sv"

module carry_look_ahead_adder_4_bit(a_in, b_in, carry_in, sum_o, carry_o);

  input [3:0]a_in;

  input [3:0]b_in;

  input carry_in;

  output [3:0]sum_o;

  output carry_o;

  wire g0, g1, g2, g3;  // Carry generate

  wire p0, p1, p2, p3;  // Carry Propogate 

  wire c0, c1, c2, c3, c4;      // Next step carry 

  wire c_1, c_2, c_3, c_4;

  assign g0 = a_in[0] & b_in[0];

  assign g1 = a_in[1] & b_in[1];

  assign g2 = a_in[2] & b_in[2];

  assign g3 = a_in[3] & b_in[3];

  assign p0 = a_in[0] ^ b_in[0]; 

  assign p1 = a_in[1] ^ b_in[1];

  assign p2 = a_in[2] ^ b_in[2]; 

  assign p3 = a_in[3] ^ b_in[3];

 // C1 = G0 + P0 · C0

 // C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0

 // C3 = G2 + P2 · C2 = G2 + P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0

 // C4 = G3 + P3 · C3 = G3 + P3 · G2 + P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0

  assign c0 = carry_in;

  assign c1 = (g0 | (p0 & c0));

  assign c2 = (g1 | (p1 & g0) | (p1 & p0 & c0));

  assign c3 = (g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c0));

  assign c4 = (g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & c0));

  full_adder FA1(.a_in(a_in[0]), .b_in(b_in[0]), .carry_in(c0), .sum_o(sum_o[0]), .carry_o(c_1));

  full_adder FA2(.a_in(a_in[1]), .b_in(b_in[1]), .carry_in(c1), .sum_o(sum_o[1]), .carry_o(c_2));

  full_adder FA3(.a_in(a_in[2]), .b_in(b_in[2]), .carry_in(c2), .sum_o(sum_o[2]), .carry_o(c_3)); 

  full_adder FA4(.a_in(a_in[3]), .b_in(b_in[3]), .carry_in(c3), .sum_o(sum_o[3]), .carry_o(c_4)); 

  assign carry_o = c4;  

endmodule

module full_adder (a_in, b_in, carry_in, sum_o, carry_o);

  input a_in;

  input b_in;

  input carry_in;

  output sum_o;

  output carry_o;

  assign sum_o = (a_in ^ b_in ^ carry_in);

  assign carry_o = (((a_in ^ b_in)& carry_in) | (a_in & b_in));

  //assign carry_o = ((a_in & b_in) | (b_in & carry_in) | (a_in & carry_in));  

endmodule

Test Bench Code:

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module carry_look_ahead_adder_16_bit_test

  reg [15:0]a_in;

  reg [15:0]b_in;

  reg carry_in;

  wire [15:0]sum_o;

  wire carry_o;

  // Instantiate design under test

  carry_look_ahead_adder_16_bit DUT(.a_in(a_in), .b_in(b_in), .carry_in(carry_in), .sum_o(sum_o), .carry_o(carry_o));   

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1);

    a_in = 16'h0000;

    b_in = 16'h0000;

    carry_in = 1'b0; 

    #10 a_in = 16'h0000; b_in = 16'h0001; carry_in = 1'b1;

    #10 a_in = 16'h0001; b_in = 16'h0001; carry_in = 1'b0; 

    #10 a_in = 16'h0010; b_in = 16'h0011; carry_in = 1'b1;

    #10 a_in = 16'h1111; b_in = 16'h1010; carry_in = 1'b0;

    #10 a_in = 16'h9001; b_in = 16'h8000; carry_in = 1'b1;

    #10 a_in = 16'h1101; b_in = 16'h1001; carry_in = 1'b0;

    #10 a_in = 16'h0001; b_in = 16'h0011; carry_in = 1'b1  

    #10 a_in = 16'h0001; b_in = 16'h0000; carry_in = 1'b0  

  end    

endmodule

Simulation Waveform:

Thanks !