Digital VLSI Design/RTL Design - Key Suggestions/Best Practices

                            

Key Suggestions/Best Practices for RTL Design

1) Always Partition Your Design into Small Blocks :

     - Partition the design into subsystems which is easy to design and test individual

     - Use Major/Minor FSMs whenever appropriate

2) Always Try to Use Same Edge Triggered Flip Flops:

     - If there are multiple clock domain , careful about passing the information from one clock domain to another clock domain

     - Proper clock domain crossing need to take place in order to corrupt any data passing between two clock domains

     - Beware of clock skew

3) Design Should be "Glitch" Free:

     - There is always glitch problem with combinations circuits

     - Never drive any critical asynchronous control signal ( Clock , Write Enable etc ) directly from the output of combinational logic

     - Whenever needed, always try to create glitch free signals by registering them

     - Always ensure a stable combinational logic output before it is sampled by clock

4) Synchronize all Asynchronous Signals:

    - Synchronize by using N-DFF ( Ex : 2-DFF Synchronizer)

5) Always Avoid Tri-State Bus Contention by Design

6) Use Asynchronous Memories Carefully:

    - Make sure write pulse is glitch free

    - Avoid any address change when Write Enable is True

    - Avoid any Z (High Impedance) address to SRAM when CE is asserted

7) During Block - to - Block Communication -

    - Might need to synchronize signals

    - Asynchronous Protocols can also be used

Thanks !