Digital Design of Full Adder (Circuit + Verilog HDL)

Full Adder:

- Adds binary numbers and accounts for values carried in as well as out.

- A 1 bit full adder adds 3 bits , two input bits to be added and one is the carry bit carried in from the previous less-significant stage.

- A 1 bit full adder adds three operands and generates 2 it results

Full Adder Block Diagram:

              

Full Adder Truth Table:

a_in	b_in	carry_in	sum_o	carry_o
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

                                               Table 1 : Full Adder Truth Table

Circuit Design of Full Adder:

Logic Expression (from Table 1 Truth Table)

sum_o = a_in' . b_in' . carry_in + a_in' . b_in . carry_in' + a_in . b_in' . carry_in' + a_in . b_in . carry_in;

sum_o = a_in' (b_in' . carry_in + _in . carry_in') + a_in (b_in' . carry_in' + b_in . carry_in);

sum_o = a_in' ( b_in ^ carry_in) + a_in ( (b_in ^ carry_in)' );

Lets assume b_in ^ carry_in = x;

sum_o = a_in' (x) + a_in (x');

sum_o = a_in ^ x;

Putting value of x;

sum_o = a_in ^ b_in ^ carry_in;

carry_o = a_in' . b_in. carry_in + a_in . b_in' . carry_in + a_in . b_in . carry_in' + a_in . b_in . carry_in;

carry_o = (a_in' . b_in + a_in . b_in'). carry_in + a_in . b_in. (carry_in' + carry_in);

carry_o = (a_in ^ b_in). carry_in + a_in . b_in ; // ( carry_in + carry_in' == 1)

Another Form of carry_o expression:

carry_o = a_in . b_in + b_in . carry_in + a_in . carry_in; // ( Get it Solving K-Map for M{3, 5, 6, 7})

Hence,

        

Full Adder Using Half Adders:

      

Verilog HDL Code:

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// Code your design here

module full_adder (a_in, b_in, carry_in, sum_o, carry_o);

  input a_in;

  input b_in;

  input carry_in;

  output sum_o;

  output carry_o;

  assign sum_o = (a_in ^ b_in ^ carry_in);

  assign carry_o = (((a_in ^ b_in)& carry_in) | (a_in & b_in));

  //assign carry_o = ((a_in & b_in) | (b_in & carry_in) | (a_in & carry_in));

endmodule

Test Bench Code:

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module full_adder_test;

  reg a_in;

  reg b_in;

  reg carry_in;

  wire sum_o;

  wire carry_o; 

  // Instantiate design under test

  full_adder DUT(.a_in(a_in), .b_in(b_in), .carry_in(carry_in), .sum_o(sum_o), .carry_o(carry_o));   

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1);

    a_in = 1'b0;

    b_in = 1'b0;

    carry_in = 1'b0;

    #10 a_in = 1'b0; b_in = 1'b0; carry_in = 1'b1; 

    #10 a_in = 1'b0; b_in = 1'b1; carry_in = 1'b0;

    #10 a_in = 1'b0; b_in = 1'b1; carry_in = 1'b1;

    #10 a_in = 1'b1; b_in = 1'b0; carry_in = 1'b0;

    #10 a_in = 1'b1; b_in = 1'b0; carry_in = 1'b1;

    #10 a_in = 1'b1; b_in = 1'b1; carry_in = 1'b0;

    #10 a_in = 1'b1; b_in = 1'b1; carry_in = 1'b1; 

    #10 a_in = 1'b0; b_in = 1'b0; carry_in = 1'b0; 

  end    

endmodule

Simulation Waveform:

 

Thanks !