Digital Design of Full Subtractor (Circuit + Verilog HDL)

 

Full Subtractor:

- A combinational circuit which is used to perform subtraction of 3 input bits

- The minued (a_in), subtrahend (b_in) and borrow input (borrow_in)

- borrow_in is set when the previous digit is borrowed from a_in

- borrow_in is subtracted from a_in as well b_in OR => (a_in - b_in - borrow_in)

- Like the half subtractor, the full subtractor generated a borrow output (borrow_o) whenever it needs to borrow from the next digit in a multi bit subtraction operation

Full Subtractor Block Daigram:

        

Full Subtractor Truth Table:

     

a_in	b_in	borrow_in	diff_o	borrow_o
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

                                    Table 1 : Full Subtractor Truth Table

Circuit Design of Full Subtractor:

Logic Expression (From Table 1 Truth Table)

diff_o = a_in' . b_in' . borrow_in + a_in' . b_in . borrow_in' + a_in . b_in' . borrow_in' + a_in . b_in . borrow_in;

diff_o = a_in' (b_in' . borrow_in + _in . borrow_in') + a_in (b_in' . borrow_in' + b_in . borrow_in);

diff_o = a_in' ( b_in ^ borrow_in) + a_in ( (b_in ^ borrow_in)' );

Lets assume b_in ^ borrow_in = x;

diff_o = a_in' (x) + a_in (x');

diff_o = a_in ^ x;

Putting value of x;

diff_o = a_in ^ b_in ^ borrow_in;

borrow_o = a_in' . b_in'. carry_in + a_in' . b_in . carry_in' + a_in' . b_in . carry_in + a_in . b_in . carry_in ;

borrow_o = (a_in' . b_in' + a_in . b_in). carry_in + a_in' . b_in (carry_in' + carry_in);

borrow_o = (a_in ^ b_in)' . carry_in + a_in' . b_in;

Hence,

          

Verilog HDL Code:

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module full_subtractor (a_in, b_in, borrow_in, diff_o, borrow_o);

  input a_in;

  input b_in;

  input borrow_in;

  output diff_o;

  output borrow_o;

  assign diff_o = (a_in ^ b_in ^ borrow_in);

  assign borrow_o = ((~(a_in ^ b_in) & borrow_in) | (~a_in & b_in));

  //assign borrow_o = ((~a_in & b_in) | (b_in & borrow_in) | (~a_in & borrow_in));

endmodule

Test Bench code:

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module full_subtractor_test;

  reg a_in;

  reg b_in;

  reg borrow_in;

  wire diff_o;

  wire borrow_o;

  // Instantiate design under test

  full_subtractor DUT(.a_in(a_in), .b_in(b_in), .borrow_in(borrow_in), .diff_o(diff_o), .borrow_o(borrow_o));        

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1);

    a_in = 1'b0;

    b_in = 1'b0;

    borrow_in = 1'b0;  

    #10 a_in = 1'b0; b_in = 1'b0; borrow_in = 1'b1;

    #10 a_in = 1'b0; b_in = 1'b1; borrow_in = 1'b0; 

    #10 a_in = 1'b0; b_in = 1'b1; borrow_in = 1'b1;

    #10 a_in = 1'b1; b_in = 1'b0; borrow_in = 1'b0;

    #10 a_in = 1'b1; b_in = 1'b0; borrow_in = 1'b1;

    #10 a_in = 1'b1; b_in = 1'b1; borrow_in = 1'b0; 

    #10 a_in = 1'b1; b_in = 1'b1; borrow_in = 1'b1;

    #10 a_in = 1'b0; b_in = 1'b0; borrow_in = 1'b0;

  end 

endmodule

Simulation Waveform:

     

Thanks !