Digital Design of Half Adder ( Circuit + Verilog HDL)

Adder:

- An Adder is a digital circuit that performs addition of given numbers

- They are used in the ALU (Arithmetic Logic Unit) circuits of computers/processors to calculate addresses , table indices and perform increment, decrement operations

Half Adder:

- Half adder adds to single binary digits say A and B. It results in two outputs called sum (S) and carry (C)

- The carry signal represents an overflow into the next digit of a multi digit addition

Half Adder Block Diagram:

                           

Truth Table of Half Adder:

                       

a_in	b_in	sum_o	carry_o
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

                                             Table 1 : Half Adder Truth Table

Circuit Design of Half Adder:

Logic Expression (From Table 1 Truth Table) -

sum_o = a_in' . b_in + a_in . b_in';

sum_o = a_in ^ b_in;

carry_o = a_in . b_in;

Hence,

Note:

- Half Adder has only two input bits and hence it can not add the carry bit coming from the lower order bits when multi bit addition is performed

- Solution - Go for Full Adder

Verilog HDL Code:

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module half_adder(a_in, b_in, sum_o, carry_o);
  input a_in;
  input b_in;
  output sum_o;
  output carry_o;
  assign sum_o = a_in ^ b_in;
  assign carry_o = a_in & b_in;
endmodule

Test Bench Code:

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module half_adder_test;

  reg a_in;

  reg b_in;

  wire sum_o;

  wire carry_o;

  

  // Instantiate design under test

  half_adder DUT(.a_in(a_in), .b_in(b_in), .sum_o(sum_o), .carry_o(carry_o));

      

  initial begin

    // Dump waves

    $dumpfile("dump.vcd");

    $dumpvars(1);

    

    a_in = 1'b0;

    b_in = 1'b0;

    

    #10 a_in = 1'b1; b_in = 1'b0;    

    

    #10 a_in = 1'b0; b_in = 1'b1;

    

    #10 a_in = 1'b1; b_in = 1'b1;

       

    #10 a_in = 1'b0; b_in = 1'b0; 

   

  end 

      

endmodule

Simulation Waveform:

Thanks !