Tic-Tac-Toe Game Design Using Python

And here comes some fun in the time when we all are locked inside our homes because of this COVID-19 pandemic ( 05/25/2020) . I am going to guide you on how you can build your own Tic_Tac_Toe Game using Python scripts in just few minutes and can enjoy playing with your loved once.How to play Tic_Tac_Toe...

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BlackJack Game Design Using Python

CASINO !!! Yes , You imagined Rightly. Let's see how in couple of minutes you can develop your own Black Jack Game using Python Scripting.Blackjack : Blackjack, formerly also Black Jack and Vingt-Un, is the American member of a global family of banking games known as "Twenty - One", whose relatives...

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Verilog HDL Examples - Design of Gray Code Counter (For FIFO Design)

Gray Code : - Named after Frank Gray- Known as reflected binary code (RBC), - Also known just as reflected binary (RB) or Gray Code - An ordering of the binary numeral system such that two successive values differ in only one bit (binary digit) Decimal(Base 10) Binary...

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Data-To-Data [Non-Sequential] Timing Checks

Data To Data Timing Checks : - Setup and hold checks between two data pins (neither of these is defined as a clock) - Also referred as Non-Sequential Constraints - One data pin is the constraint pin , like a data pin of a flop and the second pin is the related pin which acts like a clock pin of a...

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Verilog HDL Examples - FIFO Design - Asynchronous FIFOs

Asynchronous FIFO Design : - A FIFO Design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain - The clock domain are asynchronous to each other - Asynchronous FIFOs are used to safely pass the data...

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Verilog HDL Examples - FIFO Design - Synchronous FIFOs

Synchronous FIFO Design : Lets have a look at below block diagram of Synchronous FIFO. Further we will have a look at its Verilog HDL implementation.For synchronous FIFO design (a FIFO where writes to, and reads from the FIFO buffer are conducted in the same clock domain),...

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Bluetooth Low Energy - Link Layer Hardware Design : Architecture Overview

Link Layer Hardware Architecture : Lets have a look at the complete Bluetooth Low Energy (BLE) Stack Diagram below. Here, Application and Host of the BLE Stack are Software/Firmware component while Controller is a Hardware component. We will be focusing on the implementation of Link Layer (LL)...

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System Verilog Assertions - Nonconsecutive Repetition

Nonconsecutive Repetition : - Repeated, Nonconsecutive Boolean expressions can be defined using [=N] - Nonconsecutive - Not necessarily consecutive - Syntax : expr[=N]; expr must occur N times - Example : When A is high then from the same cycle , there must be two cycles of B before C ...

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System Verilog Assertions - Consecutive Repetition

Consecutive Repetition : - Repeated, consecutive sequences can be defined using [*N] - Syntax : SEQ[*N]; SEQ, repeated N times - Example : A is never low for more than 4 cycles property CONSECUTIVE_REPET; @(negedge...

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System Verilog Assertions - How it Works !!!

Here, is the flow diagram of how an assertion gets evaluated - Syntax : @(Clocking) disable iff (EXPR) enabling_sequence |=> fulfilling_sequence...

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System Verilog Assertions - Sequences

System Verilog Sequences : - Temporal properties are described using sequences - Series of Boolean equations - Each cycle separated by ## - Syntax : SEQ_A |-> SEQ_B OR SEQ_A |=> SEQ_B - Properties are either unconditional using instantaneous Boolean expression ...

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System Verilog Assertions - Example Problem

Problem: Write assertion(s) to verify the behavior of the below circuit - Solution:...

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System Verilog Assertions - Useful Built-in Functions

$past() : - Returns the value of a signal from previous evaluation cycle - Syntax : $past (A, N) ; Default N = 1 - Example : property PAST1; @(negedge CLK) EN |-> (OP == $past(IP , 2 )); endproperty ...

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System Verilog Assertions - Assertion Overlapping

Assertion Overlapping : - Assertions are checked at every evaluation point. - If the start condition is true, a new assertion is triggered. - Many copies of an assertion may be active simultaneously. Example : property A0; @(negedge CLK) REQ |=>...

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System Verilog Assertions - Example Problem

Lets have a look at below FSM Design - DATA_VALID is an input signal. DATA_READ is an output signal.Write assertions to verify the state transition from current state and inputs and outputs from current states. ( Hint: Use Implication Operators)Solution...

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