System Verilog Assertions - Example Problem

-


Problem: Write assertion(s) to verify the behavior of the below circuit -









Solution:

Comments

Post a Comment

Popular posts from this blog

Verilog HDL Examples - FIFO Design - Asynchronous FIFOs

-
Image
Asynchronous FIFO Design : - A FIFO Design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain - The clock domain are asynchronous to each other - Asynchronous FIFOs are used to safely pass the data from one clock domain to another clock domain - The main difficulty in designing the asynchronous FIFO design is related to generating the FIFO pointers and finding a reliable way to determine FULL and EMPTY status on the FIFO - Unlike synchronous FIFO Design ( here ) , the increment -decrement FIFO fill counter can not be used because two different and asynchronous clocks would be required to control the counter - We need to compare write and read pointers to determine full and empty status for an asynchronous FIFO design - The FIFO is empty when both read and write pointers are equal which happens when both pointers are reset to zero during a reset operation or when the read pointer ...
Read more

Data-To-Data [Non-Sequential] Timing Checks

-
Image
Data To Data Timing Checks : - Setup and hold checks between two data pins (neither of these is defined as a clock) - Also referred as Non-Sequential Constraints - One data pin is the constraint pin , like a data pin of a flop and the second pin is the related pin which acts like a clock pin of a flop - Below is the circuit diagram - - This check is useful in a design where it may be necessary to provide specific arrival times of one signal with respect to other - The Data-To-Data setup check is performed on the same clock edge as the launch edge - Hence, this check is also known as zero-cycle check or same-cycle check - Specifying Data-To-Data or Non-Sequential Check - Constrains can be defined in the timing library (.lib model) for a cell or can be set interactively using the set_data_check command in SDC 1) Non-Sequential check defined in the timing library - pin ( D1 ) { direction : input; timing ( ) related_pin : “D2"; timing_type : non_seq_setup_rising; ... ...
Read more

Fundamentals of Isolation Cells in Low Power VLSI Design

-
Image
In Multi Voltage VLSI Design, isolation cells play an important role in the modern VLSI world. Requirement : Lets have a look at the below diagram - - Lets assume VDDA voltage domain is always ON and VDDB voltage domain can go ON or OFF based on the certain design requirements ( To minimize the power consumption of the whole design) - When VDDB domain is OFF , the outputs of all the gates of this domain are at unpredictable state. - Since , some of the gates of VDDB domain might be driving some logic in VDDA domain (Which is always ON) but since VDDB domain signals are at unknown state (X) and they might corrupt the logic in VDDA domain and eventually the VDDA domain functionality gets corrupted - To avoid such scenario , we need to isolate the signals going from VDDB(OFF) to VDDA(ON) domain by the use of nothing but called as isolation cells - By using isolation cells we will clamp the respective logic to a proper value (0 or 1 or Latch ) Isolation cell...
Read more