System Verilog Assertions - Sequences

System Verilog Sequences :

- Temporal properties are described using sequences

- Series of Boolean equations

- Each cycle separated by ##

- Syntax : SEQ_A |-> SEQ_B OR SEQ_A |=> SEQ_B

- Properties are either unconditional using instantaneous Boolean expression

property UNCONDITIONAL:

@(posedge CLK) (COUNT >10);

endproperty

- OR , conditional using implication operators

property CONDITIONAL;

@(posedge CLK) A |=> B ##1 C;

endproperty

- If Enabling Sequence (A) is True, than only Fulfilling Sequence (B ##1 C) will Evaluate.




Disabling Properties -

- To terminate an assertion when a condition is true

- use disable iff (expr)

- If expr is true at any point of time, then the property is terminated and it Passes.

- Useful for cancelling multicycle sequence properties

- Example :

property ABORT;

@(negedge CLK) disable iff (RST)

A |=> B ##1 C ##1 D;

endproperty

assert property (ABORT);






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