Gray Code : - Named after Frank Gray- Known as reflected binary code (RBC), - Also known just as reflected binary (RB) or Gray Code - An ordering of the binary numeral system such that two successive values differ in only one bit (binary digit) Decimal(Base 10) Binary...
Thursday, July 22, 2021
Data-To-Data [Non-Sequential] Timing Checks
Data To Data Timing Checks : - Setup and hold checks between two data pins (neither of these is defined as a clock) - Also referred as Non-Sequential Constraints - One data pin is the constraint pin , like a data pin of a flop and the second pin is the related pin which acts like a clock pin of a...
Wednesday, July 21, 2021
Verilog HDL Examples - FIFO Design - Asynchronous FIFOs
Asynchronous FIFO Design : - A FIFO Design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain - The clock domain are asynchronous to each other - Asynchronous FIFOs are used to safely pass the data...
Verilog HDL Examples - FIFO Design - Synchronous FIFOs
Synchronous FIFO Design : Lets have a look at below block diagram of Synchronous FIFO. Further we will have a look at its Verilog HDL implementation.For synchronous FIFO design (a FIFO where writes to, and reads from the FIFO buffer are conducted in the same clock domain),...
Monday, July 19, 2021
Bluetooth Low Energy - Link Layer Hardware Design : Architecture Overview

Link Layer Hardware Architecture : Lets have a look at the complete Bluetooth Low Energy (BLE) Stack Diagram below. Here, Application and Host of the BLE Stack are Software/Firmware component while Controller is a Hardware component. We will be focusing on the implementation of Link Layer (LL)...
System Verilog Assertions - Nonconsecutive Repetition
Nonconsecutive Repetition : - Repeated, Nonconsecutive Boolean expressions can be defined using [=N] - Nonconsecutive - Not necessarily consecutive - Syntax : expr[=N]; expr must occur N times - Example : When A is high then from the same cycle , there must be two cycles of B before C ...
System Verilog Assertions - Consecutive Repetition
Consecutive Repetition : - Repeated, consecutive sequences can be defined using [*N] - Syntax : SEQ[*N]; SEQ, repeated N times - Example : A is never low for more than 4 cycles property CONSECUTIVE_REPET; @(negedge...
Sunday, July 18, 2021
System Verilog Assertions - How it Works !!!
Here, is the flow diagram of how an assertion gets evaluated - Syntax : @(Clocking) disable iff (EXPR) enabling_sequence |=> fulfilling_sequence...
System Verilog Assertions - Sequences
System Verilog Sequences : - Temporal properties are described using sequences - Series of Boolean equations - Each cycle separated by ## - Syntax : SEQ_A |-> SEQ_B OR SEQ_A |=> SEQ_B - Properties are either unconditional using instantaneous Boolean expression ...
System Verilog Assertions - Example Problem
Problem: Write assertion(s) to verify the behavior of the below circuit - Solution:...
System Verilog Assertions - Useful Built-in Functions
$past() : - Returns the value of a signal from previous evaluation cycle - Syntax : $past (A, N) ; Default N = 1 - Example : property PAST1; @(negedge CLK) EN |-> (OP == $past(IP , 2 )); endproperty ...
Saturday, July 17, 2021
System Verilog Assertions - Assertion Overlapping
Assertion Overlapping : - Assertions are checked at every evaluation point. - If the start condition is true, a new assertion is triggered. - Many copies of an assertion may be active simultaneously. Example : property A0; @(negedge CLK) REQ |=>...
System Verilog Assertions - Example Problem
Lets have a look at below FSM Design - DATA_VALID is an input signal. DATA_READ is an output signal.Write assertions to verify the state transition from current state and inputs and outputs from current states. ( Hint: Use Implication Operators)Solution...
System Verilog Assertions - Implication Operators
Same Cycle Implication ( |->) : Only under certain conditions assertions may be valid. exp1 |-> exp2 ; If exp1 is true then exp2 must be true at the same evaluation point.Example : property SameCyImp ...
System Verilog Assertions - Clocked Property Evaluation
Clocked Property Evaluation : Remember - "Objects are sampled before the Clock Edge"Lets have a look at below examples -1) property EN_1HOT @(EN1 or EN2) (EN1 | EN2) endproperty 2) property EN_1HOT_CLK @(psoedge CLK) (EN1 | EN2) endproperty Now, Lets have a look at the signal...
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