System Verilog Assertions - Clocked Property Evaluation

Clocked Property Evaluation :

Remember - "Objects are sampled before the Clock Edge"

Lets have a look at below examples -

1) property EN_1HOT

@(EN1 or EN2) (EN1 | EN2)

endproperty

2) property EN_1HOT_CLK

@(psoedge CLK) (EN1 | EN2)

endproperty

Now, Lets have a look at the signal waveform below -





Important Points:


1) EN_1HOT Property is evaluated whenever there is a change in EN1 or EN2 Signal ( As shown in above waveform)

2) EN_1HOT_CLK Property is evaluated at every Positive Edge of the Clock ( As shown in above waveform)

3) As you observe in the above waveform when a property evaluates, the property expression objects are evaluated before the property clocking expression ( See the point in the above waveform where EN_1HOT Fails )


Hope, this example gives an insight on how the assertion property evaluation takes place.


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