System Verilog Assertions - Assertion Overlapping

Assertion Overlapping : - Assertions are checked at every evaluation point. - If the start condition is true, a new assertion is triggered. - Many copies of an assertion may be active simultaneously. Example : property A0; @(negedge CLK) REQ |=>...

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System Verilog Assertions - Example Problem

Lets have a look at below FSM Design - DATA_VALID is an input signal. DATA_READ is an output signal.Write assertions to verify the state transition from current state and inputs and outputs from current states. ( Hint: Use Implication Operators)Solution...

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System Verilog Assertions - Implication Operators

Same Cycle Implication ( |->) : Only under certain conditions assertions may be valid. exp1 |-> exp2 ; If exp1 is true then exp2 must be true at the same evaluation point.Example : property SameCyImp ...

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System Verilog Assertions - Clocked Property Evaluation

Clocked Property Evaluation : Remember - "Objects are sampled before the Clock Edge"Lets have a look at below examples -1) property EN_1HOT @(EN1 or EN2) (EN1 | EN2) endproperty 2) property EN_1HOT_CLK @(psoedge CLK) (EN1 | EN2) endproperty Now, Lets have a look at the signal...

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System Verilog Assertions - Counterintuitive Clock Behavior

Counterintuitive Clock Behavior in Assertions: It is possible that the properties do not behave as intended. Example : Using the same signal in clocking expression and the property definition assert property (@(posedge clock) clock))...

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System Verilog Assertions - Simple Boolean Assertions

There are two kind of assertions in System Verilog :1) Immediate Assertion (Assert)2) Concurrent Assertion (Assert Property)1) Immediate Assertion: These are procedural statements (Embedded within a procedural block) and only active within the block. These are similar to the 'if' statement. Example : always @ (negedge clock ) assert !(wr_en...

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System Verilog Assertions - What & Why & Who

Assertion:What : A check embedded in the code !!! Embedded in functional code, ignored by synthesis !!!Why : 1) To check if - a) A specific condition occurs during the simulation or b) A specific sequence of events occurs ...

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Digital Low Power Design - Problems & Solutions Part#4

Here , we will discuss a digital circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption.Lets analyze the below circuit -Here, by analyzing the topology of this circuit, we can clearly see that the output...

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Digital Low Power Design - Problems & Solutions Part#3

Here , we will discuss a Circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption.Lets analyze the below circuit -Here we see that when the enable is off, the datapath operator (Multiplier and Adder) output...

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Digital Low Power Design - Problems & Solutions Part#2

Here , we will discuss a Circuit which can be optimized for low power. Lets see how this circuit may consume higher power and how can we optimize it for the low power consumption.Lets Get Started - Below is the circuit. Lets analyze how this circuit consumes more power (Assume, Adder is functional...

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Time Borrowing in VLSI Design

Time Borrowing in VLSI Design : Here is the insights on what does the terminology "Time Borrowing" mean in VLSI Design, its implementation concepts and what all problems can be solved using time borrowing concepts. Everything you need to know about time borrowing? Please go through this page.Time Borrowing...

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Digital Low Power Design - Problems & Solutions Part#1

Here we will discuss a problems which causes unnecessarily higher power consumption and can be easily handled by carefully analyzing the hardware.Problem: 1) As you see in the below figure#1 , the clock is always enabled for the D-FF and even when there is no data available, the clock is always toggling...

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Questions - Digital Design Part#5

Here, are few interview questions asked in the Frontend VLSI Design Interview Questions -1) What is Cache Memory ? What is the difference between Cache Memory and Stack Memory ?Ans:2) What is Cache Hit and Cache Miss?Ans:3) Define Cache Miss Penalty ?Ans:4) What do you mean by Level#1 and Level#2 Cache ? Which one is faster ?Ans:5) What is Write-through and Write-back terminologies in Cache ? What...

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Questions - Digital Design Part#2

Frequently asked questions in Digital/RTL Design/Verification interview questions - 1) What is a critical path in a design ? Does the maximum operating frequency of a design depends on its critical path ? Justify Ans:2) What is setup time and hold time constraints ? What is their significance ? Which one do you think is critical for estimating maximum operating frequency of a circuit?Ans:3) What...

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Questions - Digital Design Part#4

Here, are few interview questions frequently asked in Frontend and Backend VLSI Design interviews -1) What is pipelining in the processor design ?Ans:2) If the number of pipeline stages are increased, the system gets slower ? Justify !!!Ans:3) What are the advantages of a pipelined design ?Ans:4) What are the different types of hazards in pipelining ? How do you avoid them ?Ans:5) What is the difference...

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