Questions - Digital Design Part#2

Frequently asked questions in Digital/RTL Design/Verification interview questions -


1) What is a critical path in a design ? Does the maximum operating frequency of a design depends on its critical path ? Justify

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2) What is setup time and hold time constraints ? What is their significance ? Which one do you think is critical for estimating maximum operating frequency of a circuit?

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3) What is slack ? What is the significance for +ve and -ve slack for a given design path ?

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4) Why do we need setup and hold time requirements for a flip -flop ?

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5) Do Latches also have setup and hold time requirements ? if yes, please justify?

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6) Why maximum frequency of a design is decided based on only setup requirement ? Justify with logical reasoning.

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7) What are the best ways to fix setup and hold violation ? Explain pros and cons of each method.

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8) Design a flip-flop using 'n' number of latches. Find the value of 'n' to design a single bit flip-flop.

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9) For a +ve level sensitive latch, at which edge will you consider setup and hold requirements ? Suppose the enable signal for a latch is a clock signal ?

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10) How can you increase setup and hold time for a flip-flop ? Draw necessary circuit diagram.

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