System Verilog Assertions - Counterintuitive Clock Behavior

Counterintuitive Clock Behavior in Assertions:

It is possible that the properties do not behave as intended.

Example : Using the same signal in clocking expression and the property definition

assert property (@(posedge clock) clock)) -------- > This assertion always FAILS !!!

Explanation : Lest see the circuit diagram below -


 

 If you want to verify the behavior of this circuit using the assertion below -

assert property (@(posedge clock) clock)) ----- > This will always FAIL

Lets see the waveform of above circuit -
"LRM defines regions where the signals are sampled and where they are updated."


So here ,At clocking expression @(posedge clock) , the property definition (Clock) is always evaluated to False and hence this assertion always FAILS !!!


Note: Objects are sampled before Clock Edge !!!


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