System Verilog Assertions - What & Why & Who

Assertion:

What :

A check embedded in the code !!! Embedded in functional code, ignored by synthesis !!!

Why :

1) To check if -

a) A specific condition occurs during the simulation or

b) A specific sequence of events occurs

2) Significantly enhance productivity of designers by finding bugs earlier in the design and more easily

3) Assertions monitors and reports -

a) Expected design behavior

b) Protocols correctness

c) Forbidden behavior

4) Reduce debug time by identifying incorrect design behavior when and where it occurs

5) Helps designers to better understand their design

Who :

Who writes assertions -






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