System Verilog Assertions - Simple Boolean Assertions

There are two kind of assertions in System Verilog :

1) Immediate Assertion (Assert)

2) Concurrent Assertion (Assert Property)

1) Immediate Assertion: These are procedural statements (Embedded within a procedural block) and only active within the block. These are similar to the 'if' statement.

Example :

always @ (negedge clock )

assert !(wr_en && rd_en) ------- > Immediate Assertion

Note: wr_en and rd_en should never be 1 together, if so , assertion will results in failure


Equivalent Verilog Code for the above mentioned assertion :

always @ (negedge clock )

if(wr_en && rd_en)

$displey ("Error !!!");

You can code the above assertion in different ways like below -

a) assert !(wr_en && rd_en) $display ("All Good ") ;

else $display (" Error ");

b) You may only display the filing condition -

assert !(wr_rn && rd_en) else $display ("Error");

2) Concurrent Assertion: Concurrent assertions are used to specify functional property of design(A general behavior attribute used to characterize a design). They are not procedural codes and evaluated as a separate thread.

Examples of design behavior -

a) The read and write signal should never be asserted together

b) A request should be followed by an acknowledgement

1) assert property !(wr && rd)

2) assert property (@(posedge clock) Req |=> ACK )

Example: Signals wr_en and rd_en are never both high at the negedge of clock

rw_chk : assert property (@(negedge clock) !(wr_en && rd_en))

@(negedge clock) is the temporal condition for the clock expression. The design behavior is only checked on this condition

Important Notes:

1) Properties are often built using sequences

2) Concurrent assertions are checked throughout the simulation

3) Concurrent assertions usually appears outside any procedural blocks , interfaces and programs (Sometimes they may also be used as statements in initial or always block , A concurrent assertion inside initial block is only tested on first clock tick). Immediate assertions are defined within a procedural block (always or initial)

4) An immediate assertion describes a logic behavior at an instant of time while a concurrent assertion detects a behavior over a period of time


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