Bit Manipulation Circuit Design:
Design a circuit which manipulates data available in the memory and outputs them as depicted in below diagram
Solution :
Assume we have 15 words of data each having 15 bits as shown in the figure above.
Verilog HDL Code :
/////////////////////////Bit Manipulation/////////////////////////////////////////////////////////
module BitManipulation(
input Clock,
input Reset,
output [15:0] Out
);
reg [15:0]Out;
reg [15:0]Buffer[0:15]; //Available data to be manipulated
integer Nshift=0;
integer Shift=0;
wire i=0;
reg [15:0]Mask=16'h1;
reg [15:0] temp;
reg [15:0]temp1=16'h0;
parameter [2:0] reset=3'b000,
load=3'b001,
shift=3'b010,
mask=3'b011,
result=3'b100;
reg [2:0] State;
always@(posedge Clock)
begin
if(Reset)
begin
State<=reset;
Buffer[0]<=16'h0;
Buffer[1]<=16'h1;
Buffer[2]<=16'h2;
Buffer[3]<=16'h3;
Buffer[4]<=16'h4;
Buffer[5]<=16'h5;
Buffer[6]<=16'h6;
Buffer[7]<=16'h7;
Buffer[8]<=16'h8;
Buffer[9]<=16'h9;
Buffer[10]<=16'hA;
Buffer[11]<=16'hB;
Buffer[12]<=16'hC;
Buffer[13]<=16'hD;
Buffer[14]<=16'hE;
Buffer[15]<=16'hF;
end
else
begin
case(State)
reset: begin
State<=load;
end
load: begin
temp<=Buffer[Nshift];
if(Nshift==0)
begin
State<=mask;
end
else
begin
State<=shift;
end
end
shift: if(Shift<Nshift)
begin
temp<=temp<<1;
State<=shift;
Shift=Shift+1;
end
else
begin
State<=mask;
Shift<=0;
end
mask: begin
temp<=temp & Mask;
Mask<=Mask<<1;
State<=result;
Nshift=Nshift+1;
end
result: begin
temp1<=temp1|temp;
Out<=temp1;
if(Nshift==17)
begin
Nshift=0;
Mask<=16'h1;
temp1<=16'h0;
Buffer[0]<=Buffer[0]>>1;
Buffer[1]<=Buffer[1]>>1;
Buffer[2]<=Buffer[2]>>1;
Buffer[3]<=Buffer[3]>>1;
Buffer[4]<=Buffer[4]>>1;
Buffer[5]<=Buffer[5]>>1;
Buffer[6]<=Buffer[6]>>1;
Buffer[7]<=Buffer[7]>>1;
Buffer[8]<=Buffer[8]>>1;
Buffer[9]<=Buffer[9]>>1;
Buffer[10]<=Buffer[10]>>1;
Buffer[11]<=Buffer[11]>>1;
Buffer[12]<=Buffer[12]>>1;
Buffer[13]<=Buffer[13]>>1;
Buffer[14]<=Buffer[14]>>1;
Buffer[15]<=Buffer[15]>>1;
end
State<=load;
end
endcase
end
end
endmodule
Test- Bench Code :
`timescale 1ns / 1ps
module BitManipulation_TB;
// Inputs
reg Clock;
reg Reset;
// Outputs
wire [15:0] Out;
// Instantiate the Unit Under Test (UUT)
BitManipulation uut (
.Clock(Clock),
.Reset(Reset),
.Out(Out)
);
initial begin
// Initialize Inputs
Clock = 0;
Reset = 0;
// Wait 100 ns for global reset to finish
#5;
Reset=1;
#5;
Reset=0;
// Add stimulus here
end
always begin
#5 Clock=!Clock;
end
endmodule
Simulation Results :
Note: The project can be found here
-----------------------------------------------Happy Learning---------------------------------------------------
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