Static Timing Analysis - (Foundation) - Part#3

Characteristics of Timing Arc :

- Below information is derived from the timing library

1) Unateness

2) Delay

3) Slew

1) Unateness :

- How the output (of a cell) changes for different types of transition on input

- Specifies how the output is responding for a particular input and how much time it will take

- A timing arc can have 3 types of unateness

A) Positive unate :

- When rising input results in rising output OR falling input results in falling output

- Example : Buffer, AND , OR

B) Negative unate :

- When rising transition on input results in falling transition on output OR falling transition in input results in rising transition on output

- Example : Inverter, NAND, NOR

C) Non-unate :

- No relationship between input (source) and output (sink) pin

- Example : XOR, XNOR

2 ) Delay :

Cell Delay :

- The delay through a cell is determined by -

A) The intrinsic delay

B) The load that it is driving and

C) The input transition, also known as input slew

- Lets have a look at below pictures for an inverter cell -










Net Delay :

- It appears because of the resistance and the capacitance of inter-connect

- Wire-Load Models are used to calculate the net delay

- The delay is calculated based on the block area specification in WL Model




Note: Timing information for all the cells is available in liberty (.lib) files




Next : Explain the Unateness of Buffer, Inverter , AND, OR , NAND, NOR, XOR, XNOR Gates





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