AMBA (Advanced Microcontroller Bus Architecture) Specification - Questions & Answers Part#3

1) When a master rebuilds a burst which has been terminated early are there any limitations on how it rebuilds the burst?

Answer - The only limitation is that the master uses legal burst combinations to rebuild the burst. For example, if a master was performing an 8 beat burst, but had only completed 3 transfers before losing control of the bus, then the remaining 5 transfers could be performed either by using a 1 beat SINGLE burst followed by a 4 beat INCR4 burst, or it could be performed using a 5 beat undefined length INCR burst.

For simplicity it is recommended that masters use INCR bursts to rebuild the remaining transfers.

2) Why is a burst not allowed to cross a 1 kilobyte boundary?

Answer - If an AHB slave samples HSELx at the start of a burst transaction, it knows it will be selected for the duration of the burst. Also, a slave which is not selected at the start of a burst will know that it will not become selected until a new burst is started.

1 kilobyte is the smallest area an AHB slave may occupy in the memory map. Therefore, if a burst did cross a 1 kilobyte boundary, the access could start accessing one slave at the beginning of the burst and then switch to another on the boundary, which must not happen for the above reason.

The 1 kilobyte boundary has been chosen as it is large enough to allow reasonable length bursts, but small enough that peripherals can be aligned to the 1 kilobyte boundary without using up too much of the available memory map.

3) How do you connect an AHB Master to an AHB-lite system?

Answer - An AHB-lite system does not have any arbitration logic, so the full AHB master will be permanently granted. The full AHB master HBUSREQ output will be left unconnected, and the HGRANT input tied to logic '1' (1'b1).

As AHB-lite does not support SPLIT or RETRY responses, the AHB-lite HRESP signal is a single bit, so the full AHB master HRESP[1:0] input should have HRESP[1] tied to logic '0' (1'b0).

The full AHB master drives HLOCK in advance of the LOCKed transfer address phase, and this would normally be retimed in full AHB by an Arbiter module to produce HMASTLOCK, which is address phase aligned.

The following Verilog code would implement the required AHB HLOCK -> AHB-lite HMASTLOCK retiming function.

always @( negedge (HRESETn) or posedge (HCLK) )

begin

if ((!HRESETn))

HMASTLOCK <= 1'b0;

else

begin

if (HREADY)

HMASTLOCK <= HLOCK;

end

end

4) How does AHB differ from AHB-lite?

Answer - AHB-lite is a simplified version of the full AMBA 2 AHB specification, supporting only a single Master.

This removes the need for arbitration signals, HBUSREQ and HGRANT, and HRESP only needs to be 1 bit as SPLIT and RETRY slave responses are only used for multi-master support.

The removal of any arbitration logic also means the AHB Master HLOCK output (driven ahead of the LOCKed transfer address phase) needs to be retimed to be the address phase aligned HMASTLOCK signal (a function usually performed by the AHB arbiter).

5) How many clock cycles should the reset signal in an AMBA system be asserted for?

Answer - It is recommended that master and slave components should clearly state if they have a reset requirement greater than 1 or 2 cycles. It is also recommended that the system design should hold reset asserted for at least 16 cycles, unless it is known that a master or slave component has a longer reset requirement.

6) Is it legal for an AHB wrapping burst to be aligned with respect to the total number bytes in the burst, such that it does not wrap?

Answer - Yes, this behavior is compliant with the AHB protocol.

Consider a four-beat wrapping burst of word (4-byte) transfers (which will wrap at 16-byte boundaries).

If the start address of the transfer is 0x30, then the burst consists of four transfers to addresses 0x30, 0x34, 0x38, and 0x3C.

Again, although HBURST is set to WRAP4, the burst will not actually wrap, which is allowed.

7) Why is there a 1KB restriction in AHB?

Scenario -

1. What is the calculation behind this 1KB boundary.

2. Can we have more than 1KB space allocated to each slave.

Answer -

The 1KB restriction you refer to is not a restriction on maximum slave size but a constraint within AHB that says that a burst must not cross a 1KB boundary. The limit is designed to prevent bursts crossing from one device to another and to give a reasonable trade-off between burst size and efficiency. In practice, this means that a master must ALWAYS break a burst that would otherwise cross the 1KB boundary and restart it with a non-sequential transfer, thus:

Address: 0x3F0 0x3F4 0x3F8 0x3FC 0x400 0x404 0x408

Transfer: NSEQ SEQ SEQ SEQ NSEQ SEQ SEQ

There is no upper limit to the slave footprint - ARM PrimeCells, for instance, are 4KB

8) General: Why is there no wait signal on the APB?

Answer - The APB has been designed to implement as simple an interface as possible. Having this simple design makes it much easier to connect new APB peripherals and makes the analysis of the system performance easier to calculate.

Although many APB peripherals are slow devices, such as UARTs, they are normally accessed via control registers. Typically the driver software will first access a status register to determine that data is available and only then access the data register. Both of these accesses are possible without the addition of wait states and therefore the peripheral can easily be accessed as an APB device.

Peripherals which do require wait states can be designed as AHB slaves and in the rare case that a design does include a large number of these peripherals then a secondary stub AHB can be used to reduce the loading on the main system bus.

9) what is aligned data transfer?

Answer - “Address alignment” refers to the starting and ending memory address locations of the data transfer.

A data transfer is “aligned” if all of its data beats utilize all of the byte lanes of the bus.

A “data beat” is defined as a transfer of data across the bus, full width or less, in one time interval or clock cycle.

Alignment and use of all byte lanes during data transfers produces maximum bus throughput and overall system performance. In order to achieve alignment, the starting address and the total size of a transfer must be a multiple of the bus size. For example, with a 4-byte bus, aligned transfers must have a starting address that is a multiple of 4 (i.e., 0, 4, 8, etc.), and their total size must be a multiple of 4.

A data transfer is “unaligned” if one or more of its data beats does not use all of the byte lanes of the bus. In order for this to occur, either the starting address or the total size of the transfer (or both) must not be a multiple of the bus size. For example, with a 4-byte bus, if the starting address is 2 (not a multiple of 4), then the first data beat of the transfer will only use two of the bytes of the bus. Another example, again with a 4-byte bus, is a transfer of 6 bytes (again, not a multiple of 4). In this case, even if the starting address is a multiple of 4 (e.g., address 0), then the first data beat will be aligned (i.e., using all four bytes of the bus), but the second data beat will be unaligned because it will only use two of the bytes of the bus. Note that a transfer for which the starting address is not a multiple of the bus size may result in both the first and the final data beats being unaligned. For example, with a 4-byte bus, a transfer of 8 bytes with a starting address of 2 will result in: a first data beat of an unaligned transfer of 2 bytes (addresses 2 and 3), a second data beat of an aligned transfer of 4 bytes (addresses 4–7), and a final data beat of an unaligned transfer of 2 bytes (addresses 8 and 9).

Source:http://www.freepatentsonline.com/7093058.html

10) What system support is required if a slave can be powered down or have its clock stopped?

Answer - If a slave access is attempted while that slave is in a power down state or has had its clock stopped, you must ensure that an access will cause the power/clock to be restored, or else configure the AHB decoder up to redirect any such accesses to the dummy slave so that the system does not hang forever when an access to the device is made when it is disabled.

Redirecting the access in this way will ensure that random "IDLE" addresses are treated with the HREADY high and HRESP=OKAY default response, but real accesses (NONSEQ or SEQ) will be detected with an ERROR response.




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