Static Timing Analysis - (Foundation) - Part#5

Clock Skew & Clock Jitter

Clock Skew :







- Variation in the RC delay of the wire resistance and gate load causes clock to get to different elements at different times, known as clock skew.

- As shown in above example, the skew is , delta (δ) = CLK - CLK'

Note: Please refer Basics of Setup and Hold Timing Constraints before going further deep into this article to better understand the impact of Clock Skew and Clock Jitter in the circuits.




Positive Clock Skew -

- Both clock and data flow in the same direction










- Positive skew improves the performance(Tsetup) but makes it harder to meet hold requirements


Negative Clock Skew :

- Clock and Data flow in opposite direction









- Negative Clock skew degrades performance (Tsetup) but easier to meet hold requirements




Clock Jitter :












- Jitter directly reduces the performance of the sequential circuit (Tsetup)


Combined Impact of Skew (+) and Jitter :












- Positive skew with Jitter degrades performance and makes hold requirements even harder to meet

Reduce Clock Skew by -

- Careful clock distribution network design
- Plenty of metal wiring resources
- Active de-skewing
- Supply filtering




-----------------------------------------------------Happy Learning-------------------------------------