AMBA (Advanced Microcontroller Bus Architecture) Specification - Questions & Answers Part#2

1) Can HTRANS change whilst HREADY is low?

Answer - In general, an AHB master should not change control signals whilst HREADY is low. However it is allowable to change HTRANS in the following conditions:

HTRANS = IDLE

The AHB master is performing internal operations and has not yet committed to a bus transfer. However during the AHB wait states (HREADY low) the master may determine that a bus transfer is required and change HTRANS on the next cycle to NONSEQ.

HTRANS = BUSY

HTRANS is being used to give the master time to complete internal operations, which may be entirely independent of HREADY (i.e. wait states on the AHB). Therefore HTRANS can change on the next cycle to any legal value, i.e. SEQ if the burst is to continue, IDLE if the burst has completed, NONSEQ if a separate burst is to begin.

HRESP = SPLIT/RETRY

As stated in the AHB specification, a master must assert IDLE on HTRANS during the second cycle of the two-cycle SPLIT or RETRY slave response so HTRANS will change value from the first cycle to the second cycle of the response.

HRESP = ERROR

The master is permitted to change HTRANS in reaction to an ERROR response in the same way as in reaction to a SPLIT/RETRY response and cancel any further beats in the current burst (even if HBURST is indicating a defined-length burst). In this case HTRANS changes to IDLE on the second cycle of the response. Alternatively, the master is permitted to continue with the current transfers.

2) Can a BUSY transfer occur at the end of a burst?

Answer - A BUSY transfer can only occur at the end of an undefined length burst (INCR). A BUSY transfer cannot occur at the end of a fixed length burst (SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).

3) Is a default slave really necessary?

Answer - If the entire address space is defined then a default slave is not required. If, however, there are undefined areas in the memory map then it is important to ensure that a spurious access to a non-existent address location will not lock up the system. The functionality of the default slave is extremely simple and it will often make sense to implement this within the decoder.

4) Is it legal for a master to change HADDR when a transfer is extended?

Answer - If a master is indicating that it wants to do a NONSEQ or SEQ transfer then it cannot change the address during an extended transfer (when HREADY is low) unless it receives an ERROR, RETRY or SPLIT response.

If the master is indicating that it wants to do an IDLE transfer then it may change the address, but if it is indicating a BUSY transfer it can only change the address if the current undefined length burst is being terminated (with HTRANS also changing to IDLE or NONSEQ).

5) Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?

Answer - Yes, the control signals must remain constant throughout the duration of a burst.

6) The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed?

Answer - For some slaves it is acceptable to insert more than 16 wait states. For example, a serial boot ROM which is only ever accessed at initial power up could insert a larger number of wait states and it would not affect the calculation of the system performance and latency once system power up has been completed.

For other slaves a number of options exist. A SPLIT or RETRY response could be used to indicate that the slave is not yet able to perform the requested data transfer, or the slave could be accessed either in response to interrupts or after polling a status register, in either case indicating that the slave is now able to respond in an acceptable number of cycles.

7) What are the different bursts used for?

Answer - Typically a master would use wrapping bursts for cache line fills where the master wants to access the data it requires first and then it completes the burst to fetch the remaining data it requires for the cache line fill. Incrementing bursts are used by masters, such as DMA controllers, that are filling a buffer in memory which may not be aligned to a particular address boundary.

8) What is the difference between a dummy bus master and a default bus master?

Answer - The term default bus master is used to describe the master that is granted when none of the masters in the system are requesting access to the bus. Usually the bus master which is most likely to request the bus is made the default master.

The dummy bus master is a master which only performs IDLE transfers. It is required in a system so the arbiter can grant a master which is guaranteed not to perform any real transfers. The two cases when the arbiter would need to do this are when a SPLIT response is given to a locked transfer and when a SPLIT response is given and all other masters have already been SPLIT.

9) What is the recommended default value for HPROT?

Answer - Many bus masters will not be able to generate accurate protection information and for these bus masters it is recommended that the HPROT encoding shows, Non-cacheable, Non-bufferable, Privileged, Data Accesses which corresponds to HPROT[3:0] = 4'b0011.

10) What is the state of the AHB signals during reset?

Answer - The specification states that during reset the bus signals should be at valid levels. This simply means that the signals should be logic '0' or '1', but not Hi-Z. The actual logic levels driven are left up to the designer. HTRANS is the only signal specified during reset, with a mandatory value of IDLE.

It is important that HREADY is high during reset. If all slaves in the system drive HREADY high during reset then this will ensure that this is the case. However, if slaves are used which do not drive HREADY high during reset it should be ensured that a slave which does drive HREADY high is selected at reset.




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