1) Explain Wrap Beat Calculation in AHB ?
Answer - Following Tasks will Give Information About Wrap Boundary Beat Location Calculation
// wrap4_beat_info()
task wrap4_beat_info (logic [2:0] hburst,logic [31:0] haddr,logic [2:0] hsize);
if(hsize==3'b010 && hburst==`AHB_WRAP4 )
begin
if(haddr[3:2]==2'b00) wrap4_boundry_location=0 ; // No Wrap
else if(haddr[3:2]==2'b01) wrap4_boundry_location=3 ; // Wrap at 3rd Beat
else if(haddr[3:2]==2'b10) wrap4_boundry_location=2 ; // Wrap at 2nd Beat
else if(haddr[3:2]==2'b11) wrap4_boundry_location=1 ; // Wrap at 1st Beat
end
endtask : wrap4_at_info
// wrap8_beat_info()
task wrap8_beat_info (logic[2:0] hburst,logic[31:0] haddr,logic[2:0] hsize);
if(hsize==3'b010 && hburst==`AHB_WRAP8 )
begin
if(haddr[5:3]==3'b000) wrap8_boundry_location=0 ;
else if(haddr[5:3]==3'b001) wrap8_boundry_location=7 ;
else if(haddr[5:3]==3'b010) wrap8_boundry_location=6 ;
else if(haddr[5:3]==3'b011) wrap8_boundry_location=5 ;
else if(haddr[5:3]==3'b100) wrap8_boundry_location=4 ;
else if(haddr[5:3]==3'b101) wrap8_boundry_location=3 ;
else if(haddr[5:3]==3'b110) wrap8_boundry_location=2 ;
else if(haddr[5:3]==3'b110) wrap8_boundry_location=1 ;
end
endtask : wrap8_beat_info
// wrap16_at_info()
task wrap16_beat_info (logic[2:0] hburst, logic[31:0] haddr,logic[2:0] hsize);
if(hsize==3'b010 && hburst==`AHB_WRAP16 )
begin
if(haddr[7:4]==4'b0000) wrap8_boundry_location=0 ;
else if(haddr[7:4]==4'b0001) wrap8_boundry_location=15 ;
else if(haddr[7:4]==4'b0010) wrap8_boundry_location=14 ;
else if(haddr[7:4]==4'b0011) wrap8_boundry_location=13 ;
else if(haddr[7:4]==4'b0100) wrap8_boundry_location=12 ;
else if(haddr[7:4]==4'b0101) wrap8_boundry_location=11 ;
else if(haddr[7:4]==4'b0110) wrap8_boundry_location=10 ;
else if(haddr[7:4]==4'b0111) wrap8_boundry_location=9 ;
else if(haddr[7:4]==4'b1000) wrap8_boundry_location=8 ;
else if(haddr[7:4]==4'b1001) wrap8_boundry_location=7 ;
else if(haddr[7:4]==4'b1010) wrap8_boundry_location=6 ;
else if(haddr[7:4]==4'b1011) wrap8_boundry_location=5 ;
else if(haddr[7:4]==4'b1100) wrap8_boundry_location=4 ;
else if(haddr[7:4]==4'b1101) wrap8_boundry_location=3 ;
else if(haddr[7:4]==4'b1110) wrap8_boundry_location=2 ;
else if(haddr[7:4]==4'b1111) wrap8_boundry_location=1 ;
end
endtask : wrap16_beat_info
2) Comment on Burst termination after a BUSY transfer ?
Answer - After a burst has started, the master uses BUSY transfers if it requires more time before continuing with the next transfer in the burst. During an undefined length burst, INCR, the master might insert BUSY transfers and then decide that no more data transfers are required. Under these circumstances, it is acceptable for the master to then perform a NONSEQ or IDLE transfer that then effectively terminates the undefined length burst.
The protocol does not permit a master to end a burst with a BUSY transfer for fixed length bursts of type:
- Incrementing INCR4, INCR8, and INCR16.
- Wrapping WRAP4, WRAP8, and WRAP16.
These fixed length burst types must terminate with a SEQ transfer.
The master is not permitted to perform a BUSY transfer immediately after a SINGLE burst. SINGLE bursts must be followed by an IDLE transfer or a NONSEQ transfer.
3) Explain Early burst termination ?
Answer - Bursts can be terminated by either:
- Slave error response.
- Multi-layer interconnect termination.
Slave error response -
If a slave provides an ERROR response then the master can cancel the remaining transfers in the burst. However, this is not a strict requirement and it is also acceptable for the master to continue the remaining transfers in the burst. If the master cancels the remaining transfers in the burst then it must change HTRANS to indicate IDLE during the two-cycle Error response.
If the master does not complete that burst then there is no requirement for it to rebuild the burst when it next accesses that slave. For example, if a master only completes three beats of an eight-beat burst then it does not have to complete the remaining five transfers when it next accesses that slave.
Multi-layer interconnect termination -
Although masters are not permitted to terminate a burst request early, slaves must be designed to work correctly if the burst is not completed.
When a multi-layer interconnect component is used in a multi-master system then it can terminate a burst so that another master can gain access to the slave. The slave must terminate the burst from the original master and then respond appropriately to the new master if this occurs.
4) Important Points to be noted -
- It is recommended that the master terminates a locked transfer with an IDLE transfer.
- Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer must be ignored by the slave.
- When a master uses the BUSY transfer type the address and control signals must reflect the next transfer in the burst.
- If the master requires locked accesses then it must also assert the HMASTLOCK signal. This signal indicates to any slave that the current transfer sequence is indivisible and must therefore be processed before any other transfers are processed. Typically the locked transfer is used to maintain the integrity of a semaphore, by ensuring that the slave does not perform other operations between the read and write phases of a microprocessor SWP instruction. ( Read Modify Write)
- Most slaves have no requirement to implement HMASTLOCK because they are only capable of performing transfers in the order they are received. Slaves that can be accessed by more than one master, for example, a Multi-Port Memory Controller (MPMC) must implement the HMASTLOCK signal.
- The transfer size set by HSIZE must be less than or equal to the width of the data bus. For example, with a 32-bit data bus, HSIZE must only use the values 0b000, 0b001, or 0b010.
- The HSIZE signals have exactly the same timing as the address bus. However, they must remain constant throughout a burst transfer.
- All transfers in a burst must be aligned to the address boundary equal to the size of the transfer. For example, word transfers must align to word address boundaries (HADDR[1:0] = 0b00), and halfword transfers to halfword address boundaries (HADDR[0] = 0). The address for IDLE transfers must also be aligned, otherwise during simulation it is likely that bus monitors could report spurious warnings.
- During a waited transfer, the master is permitted to change the transfer type from IDLE to NONSEQ. When the HTRANS transfer type changes to NONSEQ the master must keep HTRANS constant, until HREADY is HIGH.
- During a waited transfer for a fixed length burst, the master is permitted to change the transfer type from BUSY to SEQ. When the HTRANS transfer type changes to SEQ the master must keep HTRANS constant, until HREADY is HIGH.
- Because BUSY transfers must only be inserted between successive beats of a burst, this does not apply to SINGLE bursts. Therefore this situation applies to the following burst types:
• INCR4, INCR8, and INCR16.
• WRAP4, WRAP8, and WRAP16.
- During a waited transfer for an undefined length burst, INCR, the master is permitted to change from BUSY to any other transfer type, when HREADY is LOW. The burst continues if a SEQ transfer is performed but terminates if an IDLE or NONSEQ transfer is performed.
- During a waited transfer, the master is permitted to change the address for IDLE transfers. When the HTRANS transfer type changes to NONSEQ the master must keep the address constant, until HREADY is HIGH.
- During a waited transfer, if the slave responds with an ERROR response then the master is permitted to change the address when HREADY is LOW
5 ) Explain ERROR Response –
Answer - A slave uses the ERROR response to indicate some form of error condition with the associated transfer. Usually this denotes a protection error such as an attempt to write to a read-only memory location. Although an OKAY response can be given in a single cycle, the ERROR response requires two cycles. To start the ERROR response, the slave drives HRESP HIGH to indicate ERROR while driving HREADYOUT LOW to extend the transfer for one extra cycle. In the next cycle HREADYOUT is driven HIGH to end the transfer and HRESP remains driven HIGH to indicate ERROR. The two-cycle response is required because of the pipelined nature of the bus. By the time a slave starts to issue an ERROR response then the address for the following transfer has already been broadcast onto the bus. The two-cycle response provides sufficient time for the master to cancel this next access and drive HTRANS[1:0] to IDLE before the start of the next transfer. If the slave requires more than two cycles to provide the ERROR response then additional wait states can be inserted at the start of the transfer. During this time HREADY is LOW and the response must be set to OKAY.
------------------------------------------------Happy Learning -----------------------------------------
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