AMBA (Advanced Microcontroller Bus Architecture) Specification - Questions & Answers Part#1

1) Does HWDATA have to remain stable during an extended transfer (when hready is low )?

Answer - HWDATA is guaranteed to remain at the same value when sampled at different clock edges in an extended transfer. However, it is possible that HWDATA can glitch after clock edges, returning to the same value as previously driven. It is possible to observe this behavior when using a typical synthesis design flow, where the control signals for the HWDATA output multiplexor can change during the extended transfer, but they result in the same output value being used.

2) Must a read after a write to the same address return the newly written data?

Scenario - When there is an AHB write followed by a read from the same address, should the read return the old or the new data when the read address phase is in same cycle of the write data phase?

Answer - The answer to this question is dependent on the design of the slave. A simple slave will not be buffering any data, so the returned read data will be the latest. A more complex slave could implement buffering for write data (if allowed by HPROT[2]) and so it could "snoop" the write buffer contents before returning read data, or it might just return the previously stored data regardless of what might be buffered.

3) Can a master de-assert HLOCK during a burst? (Arbitration)

Answer - The AHB specification requires that all address phase timed control signals (other than HADDR and HTRANS) remain constant for the duration of a burst. Although HLOCK is not an address phase timed signal, it does directly control the HMASTLOCK signal which is address phase timed. Therefore, HLOCK must remain high for the duration of a burst, and can only be de-asserted such that the following HMASTLOCK signal changes after the final address phase of the burst.

4) Can a master perform transfers other than IDLE when the bus was granted to it, but not requested by the master? (Arbitration)

Answer - Yes. A master can perform transfers other than IDLE when it had not requested the bus. Please note that in this case it is still recommended that the master asserts its request signal so that the arbiter does not change ownership of the bus to a lower priority master while the transfers are in progress.

5) What is the relationship between the HLOCK signal and the HMASTLOCK signal? (Arbitration)

Answer - At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of the master that is about to start driving the address bus and if HLOCK is asserted at this point then HMASTLOCK will be asserted by the arbiter for the duration of the address phase of the transfer.

6) When can the HGRANT signal change? (Arbitration)

Answer - The HGRANT signal can change in any cycle and the following cases are possible:

It is possible that the HGRANT signal may be asserted and then removed before the current transfer completes. This is acceptable because the HGRANT signal is only sampled by masters when HREADY is high.

A master can be granted the bus without requesting it.

The above point also means that it is possible to be granted the bus in the same cycle that it is requested. This can occur if the master is coincidentally granted the bus in the same cycle that it requests it.

7) When can Early Burst Termination occur?

Answer - Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note however that a master cannot decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses.

All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.

8) Can a master change the address/control signals during a waited transfer?

Answer - Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low.

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

9) Does the address have to be aligned, even for IDLE transfers?

Answer - Yes. The address should be aligned according to the transfer size (HSIZE) even for IDLE transfers. This will prevent spurious warnings from bus monitors used during simulation.

10) Is HREADY an input or an output from slaves?

Answer - An AHB slave must have the HREADY signal as both an input and an output.

HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer.

HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.

Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input.




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