Verilog HDL Design of an Event Detector:
Please refer previous article for the circuit design of an event detector ( Detects an event {onc clock cycle duration} at both raising and falling edge of an input data)
Verilog HDL Code ( For the first circuit described) -
// Module Event Detector (without input data sync in)
module event_detector_async(
input clk,
input rst,
input data_in,
output event_out
);
reg q_ff;
always @(posedge clk or negedge rst) // Register the data_in
begin
if(!rst)
q_ff <= 1'b0;
else
q_ff <= data_in;
end
assign event_out = (data_in) ^ (q_ff); // event_out Generation
endmodule
Test Bench:
// Code your testbench here
module async_event_detectotr_test;
reg clk;
reg rst;
reg data_in;
wire event_out;
//Instantiate Design Under Test
event_detector_async DUT(.clk(clk), .rst(rst), .data_in(data_in), .event_out(event_out));
//Generate a 10 ns Time Period Clock
always #5 clk = ~clk;
//Drive the DUT or Generate stimuli for the DUT
initial begin
clk = 0;
rst = 1;
data_in = 1'b0;
// Assert the Asynchronous Reset after 1 clock period
#1 rst = 0;
//Deassert the Reset
#5 rst = 1;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b1;
@(negedge clk) data_in = 1'b1;
@(negedge clk) data_in = 1'b1;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b1;
#100 $finish;
end
initial begin
// below two lines are used to show waveform
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
Waveform:
Yosys Synthesis Diagram:
Verilog HDL Code ( For the second circuit described) -
// Module Event Detector (with input data sync in)
module event_detector_sync(
input clk,
input rst,
input data_in,
output event_out
);
reg q_ff;
reg data_in_flop0, data_in_flop1;
wire data_in_synced;
always @(posedge clk or negedge rst) // Get the synced version of data_in
begin
if(!rst)
data_in_flop0 <= 1'b0;
data_in_flop1 <= 1'b0;
else
data_in_flop0 <= data_in;
data_in_flop1 <= data_in_flop0;
end
assign data_in_synced = data_in_flop1;
always @(posedge clk or negedge rst) // Register the data_in_synced
begin
if(!rst)
q_ff <= 1'b0;
else
q_ff <= data_in_synced;
end
assign event_out = (data_in_synced) ^ (q_ff); // event_out Generation
endmodule
Test Bench:
// Code your testbench here
module sync_event_detectotr_test;
reg clk;
reg rst;
reg data_in;
wire event_out;
//Instantiate Design Under Test
event_detector_sync DUT(.clk(clk), .rst(rst), .data_in(data_in), .event_out(event_out));
//Generate a 10 ns Time Period Clock
always #5 clk = ~clk;
//Drive the DUT or Generate stimuli for the DUT
initial begin
clk = 0;
rst = 1;
data_in = 1'b0;
// Assert the Asynchronous Reset after 1 clock period
#1 rst = 0;
//Deassert the Reset
#5 rst = 1;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b1;
@(negedge clk) data_in = 1'b1;
@(negedge clk) data_in = 1'b1;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b0;
@(negedge clk) data_in = 1'b1;
#100 $finish;
end
initial begin
// below two lines are used to show waveform
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
Waveform:
Yosys Synthesis Diagram:
-----------------------------------------------------Happy Learning--------------------------------------
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