Verilog HDL Examples - Design of 8*3 Priority Encoder Using Different Coding Styles

Design of 8*3 Priority Encoder :

- Compresses multiple binary inputs into a smaller number of inputs

- If two or more inputs are given at the same time, the input having the highest priority will take precedence

- Often used to control interrupts requests by acting on the highest priority interrupt input

- Truth Table:





Verilog HDL Code Using Conditional Assignment Statement:

//-----------------------------------8*3 Priority Encoder------------------------------------------//

module priority_encoder(

input [7:0] IN,

output [2:0] OUT

);

assign OUT = (IN[7] == 1'b1) ? 3'b111 :

(IN[6] == 1'b1) ? 3'b110 :

(IN[5] == 1'b1) ? 3'b101 :

(IN[4] == 1'b1) ? 3'b100 :

(IN[3] == 1'b1) ? 3'b011 :

(IN[2] == 1'b1) ? 3'b010 :

(IN[1] == 1'b1) ? 3'b001 :

(IN[0] == 1'b1) ? 3'b000 : 3'bxxx;

endmodule


Test Bench:

module priority_encoder_test;
reg [7:0] IN;
wire [2:0] OUT;
//wire q;
//wire qb;

// Instantiate design under test
priority_encoder DUT(.IN(IN), .OUT(OUT));

initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);

IN = 8'h0;

#10 IN = 8'b0001_0001;

#10 IN = 8'b1001_0001;

#10 IN = 8'b0000_1001;

#10 IN = 8'b0101_0000;

#10 IN = 8'b0000_1010;

#10 IN = 8'b0101_0101;

#10 IN = 8'b0001_0001;

#10 IN = 8'b0000_1001;

#10 IN = 8'b0001_0101;

#10 IN = 8'b0001_0011;
end
endmodule

Waveform:



Yosys Synthesis Diagram:






//----------------------------8*3 Priority Encoder Using case Statement ----------------------//

module priority_encoder(

input [7:0] IN,

output reg [2:0] OUT

);

always @*

begin

casex(IN)

8'b1xxxxxxx : OUT = 3'b111;

8'b01xxxxxx : OUT = 3'b110;

8'b001xxxxx : OUT = 3'b101;

8'b0001xxxx : OUT = 3'b100;

8'b00001xxx : OUT = 3'b011;

8'b000001xx : OUT = 3'b010;

8'b0000001x : OUT = 3'b001;

8'b00000001 :OUT = 3'b000;

default : OUT = 3'bxxx;

endcase

end

endmodule

Test Bench:

module priority_encoder_test;

reg [7:0] IN;
wire [2:0] OUT;
//wire q;
//wire qb;

// Instantiate design under test
priority_encoder DUT(.IN(IN), .OUT(OUT));

initial begin
// Dump waves
$dumpfile("dump.vcd");
$dumpvars(1);

IN = 8'h0;

#10 IN = 8'b0001_0001;

#10 IN = 8'b1001_0001;

#10 IN = 8'b0000_1001;

#10 IN = 8'b0101_0000;

#10 IN = 8'b0000_1010;

#10 IN = 8'b0101_0101;

#10 IN = 8'b0001_0001;

#10 IN = 8'b0000_1001;

#10 IN = 8'b0001_0101;

#10 IN = 8'b0001_0011;
end
endmodule

Waveform:



Yosys Synthesis Diagram:






Note: All Muxs comes in cascading fashion while implementing 8*3 priority encoder using conditional assignment statements (More Propagation Delay) while they appear in parallel when the encoder is implemented using 'case' statement (Less Propagation Delay). 

--------------------------------------------------Happy Learning-----------------------------------