Static Timing Analysis - Part#9 (Constraints)

Design Constraints:

- Constraints provide specifications that the design must meet through optimization

- Typical examples of constraints are -

1) Clock Constraints

2) External Constraints

3) Power Constraints

4) Net Delay Constraints

5) Environmental Constraints

6) Design Rules for Manufacturing

In General, the common constraints can be explained as follows -

1) Operating Constraints : set_operating_conditions

2) Wire-Load Models : set_wire_load_mode, set_wire_load_model, set_wire_loadselection_group

3) Environmental Constraints : set_drive, set_driving_cell, set_load, set_fanout_load, set_input_transition, set_port_fanout_number

4) Design Rules Constraints: set_max_capacitance, set_max_fanout, set_max_transition

5) Timing Constraints : create_clock, create_generated_clock, set_clock_latency, set_clock_transition, set_propagated_clock, set_clock_uncertainity, set_input_delay, set_output_delay

6) Power Constraints : set_max_dynamic_power, set_max_leakage_power

7) Exceptions : set_false_path, set_multicycle_path, set_disable_timing, set_max_delay




Path Exceptions :

- When we have to ask the STA tool to create exceptions to the normal timing calculations , we do that via path exceptions.

- Most common path exceptions used in the timing tools –

- - Multicycle Path

- - False Path

- - Disabling Timing Arc

- - Case Analysis

- - Path delay limits

Note: Difference between set_disable_timing and set_false_path:

- The set_disable_timing command disables a timing arc so that neither arrival time nor constraints propagate through it.

- The set_false_path command disables only the arrival time information. Constraints are not affected by this command.




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