Verilog HDL Examples - Design of Ring Counter (Circuit Design + HDL Code)

Ring Counter :

- Composed of Flip-Flops connected in a shift register manner

- Output of the last Flop-Flop is fed back to the input of first Flip-Flop, making a 'circular' or 'Ring' structure

- There are two types of ring counter -

1) Straight Ring Counter :

- Also known as one-hot counter

- The output of the last shift register is fed back to the first shift register input and circulates a single one (or zero) bit around the ring

2) Twisted Ring Counter :

- Also known as Johnson Ring Counter

- The complement of the output of the last shift register is fed back to the input of first shift register and circulates a stream of ones followed by zeros around the ring

In this blog, we will be first focusing on Straight Ring Counter Circuit Design and its HDL Code

- Below is the circuit diagram of Straight Ring Counter



- When the circuit is reset all the Flip-Flops except the one last Flip-Flop is initialized with zeros and the remaining one last flip-flop will be initialized with ONE ( By asserting the 'SET' input of Flip-Flop)

- In other words the RESET signal is connected to 'reset' pin of all the Flip-Flop except the last Flip-Flop where it will be connected to 'set' pin

- For a n bit Flip-Flop Straight Ring Counter, we have MOD-n counter , which means the counter has n different states

- Example : As shown in the circuit diagram, if we have a 4 bit counter, then the counter output pattern will repeat every 4 clock pulses


Verilog HDL Code :

// ------------4 bit Straight Ring Counter -----------------//

module straight_ring_counter #(parameter WIDTH = 4)

(

input clk,

input rst,

output reg [WIDTH-1 : 0] out

);

integer i;
always @(posedge clk or negedge rst)

begin

if(!rst)

out <= 4'h1;

else 

begin

out[WIDTH-1] <= out[0];

for(i = 0; i < WIDTH-1; i = i+1 )

begin

out[i] <= out[i+1];

end

end

end

endmodule


Test Bench:

// Code your testbench here
module ring_counter_test;
reg clk;
reg rst;
wire [3:0] out;

//Instantiate Design Under Test

straight_ring_counter #(4) DUT(.clk(clk), .rst(rst), .out(out));

//Generate a 10 ns Time Period Clock
always #5 clk = ~clk;

//Drive the DUT or Generate stimuli for the DUT

initial begin
clk = 0;
rst = 1;
// Assert the Asynchronous Reset after 1 clock period
#1 rst = 0;
//Deassert the Reset
#5 rst = 1;

#100 $finish;
end

initial begin
// below two lines are used to show waveform
$dumpfile("dump.vcd");
$dumpvars(1);
end

endmodule


Waveform:







Yosys Synthesis Diagram:

-----------------------------------------------Happy Learning-------------------------------------------