Micro-Processor Without Interlocked Pipelined Stages(MIPS)
Introduction:
MIPS (an acronym for Microprocessor without Interlocked Pipelined Stages) is a reduced instruction set computer (RISC) instruction set architecture developed by MIPS Technologies (formerly MIPS Computer Systems).
MIPS is a RISC instruction set architecture developed by several Stanford researchers in the mid-1980s. Originally, the name was an acronym for Microprocessor without Interlocked Pipeline Stages, but interlocks between pipeline stages were eventually reintroduced, probably for performance reasons as other processors became more advanced. The decision for making a processor without interlocking pipeline stages was based on performance and simplicity of design. With interlocks, operations such as integer division, which is very time-consuming, would cause other pipeline phases to wait until the execute unit was done with the division. This defeats the purpose of pipelining because it causes sections of the processor to idle. Reducing all phases to one clock cycle removes idling (however it might force the clock to be slower).
MIPS follows the classic 5-stage RISC pipeline: Instruction Fetch (IF), Instruction Decode/Operand Fetch (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). MIPS is a load-store architecture, which means that to do arithmetic on data, values must explicitly be read from memory with a special load instruction and written to memory with a store instruction, arithmetic instructions only operate on registers.
3 instruction formats:
– R-Type: Register operands (add,sub..)
– I-Type: Immediate operand (addi,lw,sw..)
– J-Type: For jumping (beq,bne,j,jl,jal..)
The Instruction Formats:
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