Verilog HDL Examples - Design of Ring Counter - Johnson (Circuit Design + HDL Code)

Johnson Ring Counter (Twisted Ring Counter):

Please visit wiki for more details on Ring Counters (Both Straight and Twister/Johnson Ring Counter)

Since, the theoretical portion is covered in above mentioned link, we will directly start with the circuit diagram of Twisted/Johnson Ring Counter





- All the Flip-Flops will be initialized with Zeros on Reset.

- The complement output of last Flip-Flop is connected to the input of first Flip-Flop

- For a n Flip-Flop Johnson counter, it is a MOD-2n Counter , which means the Johnson Counter has 2n different states (which is exactly double of the Straight Ring Counter)

- Example : As shown in the above circuit diagram, if we have a 4- bit Johnson counter, then the counter output repeats after 8 clock pulses


Verilog HDL Code :

// --------4-bit Johnson/Twisted Ring Counter---------------//

module johnson_ring_counter #(parameter WIDTH = 4)

(

input clk,

input rst,

output reg [WIDTH-1 : 0] out

);

integer i;

always@(posedge clk or negedge rst)

begin

if (!rst)

out <= 4'h0;

else

begin

out[WIDTH-1] <= ~ out[0];

for (i =0; i < WIDTH-1; i = i+1)

begin

out[i] <= out[i+1];

end

end

end

endmodule

Test Bench:

// Code your testbench here
module johnson_counter_test;
reg clk;
reg rst;
wire [3:0] out;

//Instantiate Design Under Test

johnson_ring_counter #(4) DUT(.clk(clk), .rst(rst), .out(out));

//Generate a 10 ns Time Period Clock
always #5 clk = ~clk;

//Drive the DUT or Generate stimuli for the DUT

initial begin
clk = 0;
rst = 1;
// Assert the Asynchronous Reset after 1 clock period
#1 rst = 0;
//Deassert the Reset
#5 rst = 1;

#100 $finish;
end

initial begin
// below two lines are used to show waveform
$dumpfile("dump.vcd");
$dumpvars(1);
end

endmodule

Waveform:




Yosys Synthesis Diagram:





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